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PDF CLC020ACQ Data sheet ( Hoja de datos )
| Número de pieza | CLC020ACQ | |
| Descripción | SMPTE 259M Digital Video Serializer with Integrated Cable Driver | |
| Fabricantes | National Semiconductor | |
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February 2000
CLC020
SMPTE 259M Digital Video Serializer with Integrated
Cable Driver
General Description
The CLC020 SMPTE 259M Digital Video Serializer with Inte-
grated Cable Driver is a monolithic integrated circuit that en-
codes, serializes and transmits bit-parallel digital data con-
forming to SMPTE 125M and SMPTE 267M component
video and SMPTE 244M composite video standards. The
CLC020 can also serialize other 8 or 10-bit parallel data. The
CLC020 operates at data rates from below 100 Mbps to over
400 Mbps. The serial data clock frequency is internally gen-
erated and requires no external frequency setting compo-
nents, trimming or filtering*. Functions performed by the
CLC020 include: parallel-to-serial data conversion, data en-
coding using the polynomial (X9+X4+1), data format conver-
sion from NRZ to NRZI, parallel data clock frequency multi-
plication and encoding with the serial data, and coaxial cable
driving. Input for sync (TRS) detection disabling and a PLL
lock detect output are provided. The CLC020 has an exclu-
sive built-in self-test (BIST) and video test pattern generator
(TPG) with 4 component video test patterns, reference
black, PLL and EQ pathologicals and modified colour bars, in
4:3 and 16:9 raster and both NTSC and PAL formats*. Sepa-
rate power pins for the output driver, VCO and the digital
logic improve power supply rejection, output jitter and noise
performance.
The CLC020 is the ideal complement to the CLC011B
SMPTE 259M Serial Digital Video Decoder, CLC014 Active
Cable Equalizer, CLC016 Data Retiming PLL (clock-data
separator), CLC018 8X8 Digital Crosspoint Switch and
CLC006 or CLC007 Cable Drivers, for a complete
parallel-serial-parallel, high-speed data processing and
transmission system.
The CLC020 is powered from a single 5V supply. Power dis-
sipation is typically 235 mW including two 75Ω
back-matched output loads. The device is packaged in a
JEDEC 28-lead PLCC.
Features
n SMPTE 259M serial digital video standard compliant
n No external serial data rate setting or VCO filtering
components required*
n Built-in self-test (BIST) and video test pattern generator
(TPG) with 16 internal patterns*
n Supports all NTSC and PAL standard component and
composite serial video data rates
n HCMOS/TTL-compatible data and control inputs and
outputs
n 75Ω ECL-compatible, differential, serial cable-driver
outputs
n Fast VCO lock time: <75 µs
n Single +5V TTL or −5V ECL supply operation
n Low power: 235 mW typical
n 28-lead PLCC package
n Commercial temperature range 0˚C to +70˚C
Applications
n SMPTE 259M parallel-to-serial digital video interfaces
for:
— Video cameras
— VTRs
— Telecines
— Video test pattern generators and digital video test
equipment
n Non-SMPTE video applications
n Other high data rate parallel/serial video and data
systems
* Patents applications made or pending.
Typical Application
DS100917-12
© 2000 National Semiconductor Corporation DS100917
www.national.com
1 page  
Test Loads (Continued)
Timing Diagram
FIGURE 2. Test Circuit
DS100917-4
FIGURE 3. Setup and Hold Timing
DS100917-5
Device Operation
The CLC020 SMPTE 259M Digital Video Serializer is used in
digital video signal origination and processing equipment:
cameras, video tape recorders, telecines, video test equip-
ment and others. It converts parallel component or compos-
ite digital video signals into serial format. Logic levels within
this equipment are normally TTL-compatible as produced by
CMOS or bipolar logic devices. The encoder outputs
ECL-compatible serial digital video (SDV) signals conform-
ing to SMPTE 259M-1997. The CLC020 operates at all stan-
dard SMPTE and ITU-R parallel data rates.
5 www.national.com
5 Page 
Application Information (Continued)
Connect LOCK DETECT to TPG ENABLE for test pattern generator function.
Remove RP1 & RP3 and replace RP2 & RP4 with 50Ω resistor packs for coax interfacing.
Install RP1-4 when using ribbon cable for input interfacing.
This board is designed for use with TTL power supplies only.
For optional ECL compatible load: R1A = R2A = 187; R1B = R2B = 124.
All resistances & impedances in Ohms. Values with 3 significant digits are 1%; with 2 digits 5%.
DS100917-9
FIGURE 7. SD020EVK Schematic Diagram
MEASURING JITTER
The test method used to obtain the timing jitter value given in
the AC Electrical Specification table is based on procedures
and equipment described in SMPTE RP 192-1996. The rec-
ommended practice discusses several methods and indica-
tor devices. An FFT method performed by standard video
test equipment was used to obtain the data given in this data
sheet. As such, the jitter characteristics (or jitter floor) of the
measurement equipment, particularly the measurement ana-
lyzer, become integral to the resulting jitter value. The
method and equipment were chosen so that the test can be
easily duplicated by the design engineer using most stan-
dard digital video test equipment. In so doing, similar results
should be achieved. The intrinsic jitter floor of the CLC020’s
PLL is approximately 25% of the typical jitter given in the
electrical specifications. In production, device jitter is mea-
sured on automatic IC test equipment (ATE) using a different
method compatible with that equipment. Jitter measured us-
ing this ATE yields values approximately 50% of those ob-
tained using the video test equipment.
The jitter test setup used to obtain values quoted in the data
sheet consists of:
• National Semiconductor SD020EVK, CLC020 evaluation
kit
• Tektronix TG2000 signal generation platform with DVG1
option
• Tektronix VM700T Option 1S Video Measurement Set
• Tektronix TDS 794D, Option C2 oscilloscope
• Tektronix P6339A passive probe
• 75 Ohm coaxial cable, 3ft., Belden 8281 or RG59 (2 re-
quired)
• ECL-to-TTL/CMOS level converter/amplifier, Figure 9
Apply the black-burst reference clock from the TG2000 sig-
nal generator’s BG1 module 27MHz clock output to the level
converter input. The clock amplitude converter schematic is
shown in Figure 9. Adjust the input bias control to give a 50%
duty cycle output as measured on the oscilloscope/probe
system. Connect the level translator to the SD020EVK
board, connector P1, PCLK pins (the outer-most row of pins
is ground). Configure the SD020EVK to operate in the NTSC
colour bars, BIST mode. Configure the VM700T to make the
jitter measurement in the jitter FFT mode at the frame rate
11 www.national.com
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet CLC020ACQ.PDF ] | |
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