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CLC020 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer CLC020
Beschreibung SMPTE 259M Digital Video Serializer with Integrated Cable Driver
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 15 Seiten
CLC020 Datasheet, Funktion
February 2000
CLC020
SMPTE 259M Digital Video Serializer with Integrated
Cable Driver
General Description
The CLC020 SMPTE 259M Digital Video Serializer with Inte-
grated Cable Driver is a monolithic integrated circuit that en-
codes, serializes and transmits bit-parallel digital data con-
forming to SMPTE 125M and SMPTE 267M component
video and SMPTE 244M composite video standards. The
CLC020 can also serialize other 8 or 10-bit parallel data. The
CLC020 operates at data rates from below 100 Mbps to over
400 Mbps. The serial data clock frequency is internally gen-
erated and requires no external frequency setting compo-
nents, trimming or filtering*. Functions performed by the
CLC020 include: parallel-to-serial data conversion, data en-
coding using the polynomial (X9+X4+1), data format conver-
sion from NRZ to NRZI, parallel data clock frequency multi-
plication and encoding with the serial data, and coaxial cable
driving. Input for sync (TRS) detection disabling and a PLL
lock detect output are provided. The CLC020 has an exclu-
sive built-in self-test (BIST) and video test pattern generator
(TPG) with 4 component video test patterns, reference
black, PLL and EQ pathologicals and modified colour bars, in
4:3 and 16:9 raster and both NTSC and PAL formats*. Sepa-
rate power pins for the output driver, VCO and the digital
logic improve power supply rejection, output jitter and noise
performance.
The CLC020 is the ideal complement to the CLC011B
SMPTE 259M Serial Digital Video Decoder, CLC014 Active
Cable Equalizer, CLC016 Data Retiming PLL (clock-data
separator), CLC018 8X8 Digital Crosspoint Switch and
CLC006 or CLC007 Cable Drivers, for a complete
parallel-serial-parallel, high-speed data processing and
transmission system.
The CLC020 is powered from a single 5V supply. Power dis-
sipation is typically 235 mW including two 75
back-matched output loads. The device is packaged in a
JEDEC 28-lead PLCC.
Features
n SMPTE 259M serial digital video standard compliant
n No external serial data rate setting or VCO filtering
components required*
n Built-in self-test (BIST) and video test pattern generator
(TPG) with 16 internal patterns*
n Supports all NTSC and PAL standard component and
composite serial video data rates
n HCMOS/TTL-compatible data and control inputs and
outputs
n 75ECL-compatible, differential, serial cable-driver
outputs
n Fast VCO lock time: <75 µs
n Single +5V TTL or −5V ECL supply operation
n Low power: 235 mW typical
n 28-lead PLCC package
n Commercial temperature range 0˚C to +70˚C
Applications
n SMPTE 259M parallel-to-serial digital video interfaces
for:
— Video cameras
— VTRs
— Telecines
— Video test pattern generators and digital video test
equipment
n Non-SMPTE video applications
n Other high data rate parallel/serial video and data
systems
* Patents applications made or pending.
Typical Application
DS100917-12
© 2000 National Semiconductor Corporation DS100917
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CLC020 Datasheet, Funktion
Device Operation (Continued)
VIDEO DATA PROCESSING CIRCUITS
The input data register accepts 8 or 10-bit parallel data and
clock signals having CMOS/TTL-compatible signal levels.
Parallel data may conform to any of several standards:
SMPTE 125M, SMPTE 267M, SMPTE 244M or ITU-R
BT.601. If data is 8-bit, it is converted to a 10-bit representa-
tion according to the type of data being input: component
4:2:2 per SMPTE 259M paragraph 7.1.1, composite NTSC
per paragraph 8.1.1 or composite PAL per paragraph 9.1.1.
Output from this register feeds the SMPTE polynomial
generator/serializer and sync detector. All CMOS inputs in-
cluding the PCLK input have internal pull-down devices.
The sync detector or TRS character detector accepts data
from the input register. The detection function is controlled
by Sync Detect Enable, a low-true, TTL-compatible, external
signal. Synchronization words, the timing reference signals
(TRS), start-of-active-video (SAV) and end-of-active-video
(EAV) are defined in SMPTE 125M-1995 and 244M. The
sync detector supplies control signals to the SMPTE polyno-
mial generator that identify the presence of valid video data.
The sync detector performs input TRS character
LSB-clipping as prescribed in ITU-R-BT.601. LSB-clipping
causes all TRS characters with a value between 000h and
003h to be forced to 000h and all TRS characters with a
value between 3FCh and 3FFh to be forced to 3FFh. Clip-
ping is done prior to encoding.
The SMPTE polynomial generator accepts the parallel
video data and encodes it using the polynomial X9+X4+1 as
specified in SMPTE 259M–1997, paragraph 5 and Annex C.
The scrambled data is then serialized for output.
The NRZ-to-NRZI converter accepts serial NRZ data from
the SMPTE polynomial genertor and converts it to NRZI us-
ing the polynomial X + 1 per SMPTE 259M–1997, paragraph
5.2 and Annex C. The transmission bit order is LSB first, per
paragraph 6. The converter’s output feeds the output driver
amplifier.
PHASE-LOCKED LOOP AND VCO
The phase-locked loop (PLL) system generates the output
serial data clock at 10x the parallel data clock frequency.
This system consists of a VCO, divider chain,
phase-frequency detector and internal loop filter. The VCO
free-running frequency is internally set. The PLL automati-
cally generates the appropriate frequency for the serial clock
rate using the parallel data clock (PCLK) frequency as its ref-
erence. Loop filtering is internal to the CLC020. The VCO
has separate VSSO and VDDO power supply feeds, pins 15
and 16, which may be supplied power independently via an
external low-pass filter, if desired. The PLL acquisition (lock)
time is less than 75 µs @ 270 Mbps.
LOCK DETECT
The Lock Detect output of the phase-frequency detector in-
dicates the PLL lock condition. It is a logic HIGH when the
loop is locked. The output is CMOS/TTL-compatible and is
suitable for driving other CMOS devices or a LED indicator.
SERIAL DATA OUTPUT BUFFER
The current-mode serial data outputs provide low-skew
complimentary or differential signals. The output buffer de-
sign can drive 75coaxial cables (AC-coupled) or 10k/100k
ECL/PECL-compatible devices (DC-coupled). Output levels
are 800 mVP-P ±10% into 75AC-coupled, back-matched
loads. The output level is 400 mVP-P ±10% when
DC-coupled into 75(See Application Information for de-
tails). The 75resistors connected to the SDO outputs are
back-matching resistors. No series back-matching resistors
should be used. SDO output levels are controlled by the
value of RREF connected to pin 19. The value of RREF is nor-
mally 1.69 k, ±1%. The output buffer is static when the de-
vice is in an out-of-lock condition. Separate VSSSD and
VDDSD power feeds, pins 21 and 24, are provided for the se-
rial output driver.
POWER-ON RESET
The CLC020 has an internally controlled, automatic,
power-on reset circuit. This circuit clears TRS detection cir-
cuitry, all latches, registers, counters and polynomial genera-
tors and disables the serial output. The SDO outputs are
tri-stated during power-on reset. The part will remain in the
reset condition until the parallel input clock is applied.
BUILT-IN SELF-TEST (BIST)
The CLC020 has a built-in self-test (BIST) function. The
BIST performs a comprehensive go-no-go test of the device.
The test uses either a full-field color bar for NTSC or a PLL
pathological for PAL as the test data pattern. Data is input in-
ternally to the input data register, processed through the de-
vice and tested for errors. Table 1 gives device pin functions
and Table 2 gives the test pattern codes used for this func-
tion. The signal level at Test_Output, pin 26, indicates a pass
or fail condition.
The BIST is initiated by applying the code for the desired
BIST to D0 throught D3 (D9 through D4 are 00h) and a
27 MHz clock at the PCLK input. Since all parallel data inputs
are equipped with an internal pull-down device, only those
inputs D0 through D3 which require a logic-1 need be pulled
high. After the Lock_Detect output goes high (true) indicating
the VCO is locked on frequency, TPG_Enable, pin 17, is then
taken to a logic high. TPG_Enable may be temporarily con-
nected to the Lock_Detect output to automate BIST opera-
tion. Test_Output, pin 26, is monitored for a pass/fail indica-
tion. If no errors have been detected, this output will go to a
logic high level approximately 2 field intervals after
TPG_Enable is taken high. If errors have been detected in
the internal circuitry of the CLC020, Test_Output will remain
low until the test is terminated. The BIST is terminated by
taking TPG_Enable to a logic low. Continuous serial data
output is available during the test.
TEST PATTERN GENERATOR
The CLC020 features an on-board test pattern generator
(TPG). Four full-field component video test patterns for both
NTSC and PAL standards, and 4x3 and 16x9 raster sizes are
produced. The test patterns are: flat-field black, PLL patho-
logical, equalizer (EQ) pathological and a modified 75%,
8-color vertical bar pattern. The pathologicals follow recom-
mendations contained in SMPTE RP 178–1996 regarding
the test data used. The color bar pattern does not incorpo-
rate bandwidth limiting coding in the chroma and luma data
when transitioning between the bars. For this reason, it may
not be suitable for use as a visual test pattern or for input to
video D-to-A conversion devices unless measures are taken
to restrict the production of out-of-band frequency compo-
nents.
The TPG is operated by applying the code for the desired
test pattern to D0 through D3 (D4 through D9 are 00h). Since
all parallel data inputs are equipped with an internal
pull-down device, only those inputs D0 through D3 which re-
quire a logic-1 need be pulled high. Next, apply a 27 or
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CLC020 pdf, datenblatt
Application Information (Continued)
with 1kHz filter bandwidth and Hanning window. Configure
the setup as shown in Figure 8. Switch the test equipment on
(from standby mode) and allow all equipment temperatures
stabilize per manufacturer’s recommendation. Measure the
jitter value after allowing the instrument’s reading to stabilize
(about 1 minute). Consult the VM700T Video Measurement
Set Option 1S Serial Digital Measurements User Manual
(document number 071-0074-00) for details of equipment
operation.
The VM700T measurement system’s jitter floor specification
at 270Mbps is given as 200ps ±20% (100ps ±5% typical) of
actual components from 50Hz to 1MHz and 200ps +60%,
-30% of actual components from 1MHz to 10MHz. To obtain
the actual residual jitter of the CLC020, a root-sum-square
adjustment of the jitter reading must be made to compensate
for the measurement system’s jitter floor specification. For
example, if the jitter reading is 250ps, the CLC020 residual
jitter is the square root of (2502 − 2002) = 150ps. The accu-
racy limits of the reading as given above apply.
FIGURE 8. Jitter Test Circuit
DS100917-10
FIGURE 9. ECL-to-TTL/CMOS level converter/amplifer
DS100917-13
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