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PDF CLC018AJVJQ Data sheet ( Hoja de datos )
| Número de pieza | CLC018AJVJQ | |
| Descripción | 8 x 8 Digital Crosspoint Switch/ 1.4 Gbps | |
| Fabricantes | National Semiconductor | |
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October 1998
CLC018
8 x 8 Digital Crosspoint Switch, 1.4 Gbps
General Description
National’s Comlinear CLC018 is a fully differential 8x8 digital
crosspoint switch capable of operating at data rates exceed-
ing 1.4 Gbps per channel. Its non-blocking architecture uti-
lizes eight independent 8:1 multiplexers to allow each output
to be independently connected to any input and any input to
be connected to any or all outputs. Additionally, each output
can be individually disabled and set to a high-impedance
state. This TRI-STATE® feature allows flexible expansion to
larger switch array sizes.
Low channel-to-channel crosstalk allows the CLC018 to pro-
vide superior all-hostile jitter of 50 psPP. This excellent signal
fidelity along with low power consumption of 850 mW make
the CLC018 ideal for digital video switching plus a variety of
data communication and telecommunication applications.
The fully differential signal path provides excellent noise im-
munity, and the I/Os support ECL and PECL logic levels. In
addition, the inputs may be driven single-ended or differen-
tially and accept a wide range of common mode levels in-
cluding the positive supply. Single +5V or −5V supplies or
dual +5V supplies are supported. Dual supply mode allows
the control signals to be referenced to the positive supply
(+5V) while the high-speed I/O remains ECL compatible.
The double row latch architecture utilized in the CLC018 al-
lows switch reprogramming to occur in the background dur-
ing operation. Activation of the new configuration occurs with
a single “configure” pulse. Data integrity and jitter perfor-
mance on unchanged outputs are maintained during recon-
figuration. Two reset modes are provided. Broadcast reset
results in all outputs being connected to input port DI0.
TRI-STATE Reset results in all outputs being disabled.
The CLC018 is fabricated on a high-performance BiCMOS
process and is available in a 64-lead plastic quad flat pack
(PQFP).
Features
n Fully differential signal path
n Non-Blocking
n Flexible expansion to larger array sizes with very low
power
n Single +5/−5V or dual ±5V operation
n TRI-STATE outputs
n Double row latch architecture
n 64-lead PQFP package
Applications
n Serial digital video routing (SMPTE 259M)
n Telecom/datacom switching
n ATM SONET
Key Specifications
n High speed: >1.4 Gbps
n Low jitter:
<50 psPP for rates <500 Mbps
<100 psPP for rates <1.4 Gbps
n Low power; 850 mW with all outputs active
n Fast output edge speeds: 250 ps
CLC018 Block Diagram
© 1998 National Semiconductor Corporation DS100088
DS100088-2
DS100088-1
www.national.com
1 page  
Connection Diagram
DS100088-9
Order Number CLC018AJVJQ
See NS Package Number VJE64A
Pin Descriptions
POWER PINS
VCC is the most positive rail for the data path. When the data
levels are ECL compatible, then VCC should be connected to
GND. For PECL data (+5V referenced ECL), VCC is con-
nected to the +5V supply. Please refer to the device opera-
tion section in this datasheet for recommendations on the
bypassing and ground/power plane requirements of this de-
vice.
VEE is the most negative rail for the data path. When the data
levels are ECL compatible, then VEE is connected to a −5.2V
power supply. For PECL data (+5V referenced ECL), VEE is
connected to GND.
VLL is the logic-level power supply. If the control signals are
referenced to +5V, VLL is connected to a +5V supply. If con-
trol signals are ECL compatible, VLL is connected to GND.
DATA INPUT PINS
DI0 and DI0 through DI7 and D17 are the data input pins to
the CLC018. Depending upon how the Power pins are con-
nected (please refer to the Power Pin section above) the
data may be either differential ECL, or differential PECL. To
drive the CLC018 inputs with a single-ended signal, please
refer to the section “Using Single-Ended Data” in the OP-
ERATION section of this datasheet.
DATA OUTPUT PINS
DO0 and DO0 through DO7 and DO7 are the data output
pins of the CLC018. The CLC018 outputs are differential cur-
rent outputs which can be converted to ECL or PECL com-
patible outputs through the use of load resistors. Please re-
fer to the “Output Interfacing” paragraph in the OPERATION
section of this datasheet for more details.
CONTROL PINS
IA2, IA1 and IA0 are the three bit input selection address
bus. The input port to be addressed is placed on this bus.
IA2 is the Most Significant Bit (MSB). If input port 6 is to be
addressed, IA2, IA1, IA0 should have 1, 1, 0 asserted on
them. The IA bus should be driven with CMOS levels, if VLL
is +5V. These levels are thus +5V referenced (standard
CMOS). If VLL is connected to GND, the input levels are ref-
erenced to the −5V and GND supplies.
OA2, OA1 and OA0 are the output selection address bus.
The output port selected by the OA bus is connected to the
input port selected on the IA bus when the data is loaded into
the configuration registers. OA2 is the MSB. If OA2, OA1,
OA0 are set to 0, 0, 1; then output port 1 will be selected.
CS is an active-high chip select input. When CS is high, the
RES, LOAD, and CNFG pins will be enabled.
LOAD is the latch control for the LOAD register. When LOAD
is high, the load register is transparent. Outputs follow the
state of the IA bus, and are presented to the inputs of the
Configuration register selected by the OA bus. When LOAD
is low, the outputs of the Load register are latched.
RES is the reset control of the configuration and load regis-
ters. A high-going pulse on the RES pin programs the switch
matrix to one of two possible states: with TRI low, all outputs
are connected to input #0; with TRI high, all outputs are put
in TRI-STATE condition.
TRI will program the selected output to be in a high imped-
ance or TRI-STATE condition. To place an output in
TRI-STATE, assert a logic-high level on the TRI input when
the desired input and output addresses are asserted on the
respective address inputs and strobe the LOAD input as de-
picted in the ”Configuration Truth Table”. To enable an out-
put, assert a logic-low level on the TRI input together with the
appropriate addresses and strobe the LOAD input as previ-
ously described.
CNFG is the configuration register latch control. When
CNFG is high the Configuration register is made transparent,
and the switch matrix is set to the state loaded into the Load
registers. When CNFG is low, the state of the switch matrix
is latched.
5 www.national.com
5 Page 
Operation (Continued)
DS100088-20
FIGURE 10. 8 x 16 Crosspoint Example
EXPANDING THE NUMBER OF INPUT PORTS
Expanding the number of inputs in a switch array is accom-
plished by wire-ORing the outputs together, and TRI-
STATEing the outputs of the CLC018s that do not have their
inputs selected. The output bus should be a controlled im-
pedance transmission line with proper termination. This is
shown in Figure 11. The circuit uses a 1-of-2 decoder with
complemented outputs to control the TRI pins of the
CLC018s in the array. Thus, all CLC018s are programmed
simultaneously, and all of them, except for the one with the
selected input, are placed in the TRI-STATE mode.
EXPANDING BOTH INPUTS AND OUTPUTS
To increase both the number of inputs and outputs in an ar-
ray, apply both the input port and output port expansion tech-
niques simultaneously. In Figure 12, this is shown for the
case of a 24 input by 32 output switch array. Note that both
input and output busses need to be controlled impedance
transmission lines. The CS pins for rows of CLC018s are
connected together and become the row select inputs,
whereas the TRI pins are connected together for the col-
umns of CLC018s and become the column select pins.
11 www.national.com
11 Page | ||
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