Datenblatt-pdf.com


CLC011BCQ Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer CLC011BCQ
Beschreibung Serial Digital Video Decoder
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 8 Seiten
CLC011BCQ Datasheet, Funktion
January 1999
CLC011
Serial Digital Video Decoder
General Description
National’s Comlinear CLC011, Serial Digital Video Decoder,
decodes and descrambles SMPTE 259M standard Serial
Digital Video datastreams with serial clock into 10-bit parallel
words and a corresponding word-rate clock. SMPTE 259M
standard parallel data is encoded and scrambled using a
9-bit shift register and is also converted from NRZ to NRZI.
The CLC011 restores the original parallel data by reversing
the encoding process. The CLC011 also extracts timing in-
formation embedded in the SDV data. These reserved code
words, known as Timing Reference Signals (TRS), indicate
the start and end of each active video line. By decoding the
TRS, the CLC011 correctly identifies the word boundaries of
the encoded input data. Detection of the TRS reserved
codes is indicated by low-true signals at the TRS and End of
Active Video (EAV) outputs.
The CLC011’s design using current-mode logic (CML) re-
duces noise injection into the power supply thereby easing
board layout and interfacing. The CMOS compatible outputs,
which feature controlled rise and fall times, may be set for ei-
ther 3.3V or 5V swings with the VDP and VCP inputs.
The CLC011 Serial Digital Video Decoder, CLC014 Adaptive
Cable Equalizer and the CLC016 Data Retiming PLL com-
bine to provide a complete Serial Digital Video receiver sys-
tem.
The CLC011 is packaged in a 28-pin PLCC.
Features
n Data decoding and deserializing
n CLC011B operates to 360Mbps
n CLC011A operates to 300Mbps
n Low noise injection to power supplies
n Single +5V or −5.2V supply operation
n Output levels programmable for interface to 5V or 3.3V
logic
n Low power
n Low cost
Block Diagram
© 1999 National Semiconductor Corporation DS100086
DS100086-1
www.national.com






CLC011BCQ Datasheet, Funktion
Input Interfacing — Control Inputs
(Continued)
FE is normally conditioned in one of three ways.
1. FE tied high. This is the most common mode for FE. In
this mode, when a TRS is received, PCLK is aligned to
the new TRS. If a new sync position (NSP) is identified,
the NSP output will go high until the next TRS is re-
ceived.
2. FE tied to NSP. When in this mode, if a TRS that is out
of phase with the existing PCLK is detected, NSP will go
high, but the phase of PCLK will not be adjusted. If the
next TRS received is in-phase with PCLK, NSP will go
low and the decoder will continue without changing its
state. If the next TRS to arrive is out of phase with PCLK,
then PCLK’s phase is adjusted to meet the new TRS
and NSP is made low. Single erroneous TRS pulses are
ignored in this mode, but if they persist, the decoder will
re-adjust PCLK to properly frame the data.
3. FE held low during active video. The automatic fram-
ing feature using the TRS may be disabled in cases
where non-SMPTE 259M signals are being processed.
In some applications like computer-generated anima-
tion, the serial video data may not adhere to the SMPTE
259M standard and patterns that resemble TSR’s can
occur within the active video line. When such patterns
occur and to prevent the CLC011 from attempting re-
framing, make FE a logic low during the active video
line.
Output Interface — Output Logic
Levels
All outputs of the CLC011 are CMOS compatible. They can
be programmed to provide appropriate output logic levels to
connect to following stages operating from supplies of 3.0V
to 5.5V. Output voltages are set by applying the positive sup-
ply voltage powering the following stage to VDP, which con-
trols PD0-9, EAV, TRS and NSP, and VCP, which controls
PCLK. An example of the CLC011, powered from +5V, driv-
ing a device powered from a 3.3V supply is shown in Figure
5.
The CLC011’s output drivers, shown simplified in Figure 6,
are designed to maintain a constant, controlled slew rate re-
gardless of load. This design results in lower output switch-
ing noise injection via the supply pins and into other circuitry.
Even so, it is recommended that the CLC011 and other digi-
tal circuitry be separated from analog circuitry and cable
equalizers.
DS100086-8
FIGURE 6. Simplified Output Buffer Schematic
DS100086-7
FIGURE 5. Typical Output Interface
www.national.com
6

6 Page







SeitenGesamt 8 Seiten
PDF Download[ CLC011BCQ Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
CLC011BCQSerial Digital Video DecoderNational Semiconductor
National Semiconductor

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche