PDF ADSP-SC582 Data sheet ( Hoja de datos )

Número de pieza	ADSP-SC582
Descripción	SHARC+ Dual Core DSP
Fabricantes	Analog Devices
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SHARC+ Dual Core DSP with ARM Cortex-A5 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 SYSTEM FEATURES Dual enhanced SHARC+ high performance floating-point cores Up to 450 MHz per SHARC+ core Up to 5 Mbits (640 kB) L1SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short-word, word, long-word addressed ARM Cortex-A5 core 450 MHz/720 DMIPS with Neon/VFPv4-D16/Jazelle 32 kB L1 instruction cache/32 kB L1 data cache 256 kB L2 cache with parity Powerful DMA system On-chip memory protection Integrated safety features 19 mm × 19 mm 349/529 BGA (0.8 pitch), RoHS compliant Low system power across automotive temperature range MEMORY Large on-chip L2 SRAM with ECC protection, up to 256 kB On-chip L2 ROM (512 kB) Two L3 interfaces optimized for low system power, providing 16-bit interface to DDR3, DDR2 or LPDDR1 SDRAM devices ADDITIONAL FEATURES Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Support for TrustZone® Accelerators High performance pipelined FFT/IFFT engine FIR, IIR, HAE, SINC offload engines SYSTEM CONTROL SECURITY AND PROTECTION SYSTEM PROTECTION (SPU) SYSTEM MEMORY PROTECTION UNIT (SMPU) FAULT MANAGEMENT ARM® TrustZone® SECURITY DUAL CRC WATCHDOGS OTP MEMORY THERMAL SENSOR PROGRAM FLOW SYS EVENT CONTROLLER (SEC) TRIGGER ROUTING (TRU) CLOCK, RESET, AND POWER CLOCK GENERATION (CGU) CLOCK DISTRIBUTION UNIT (CDU) REAL TIME CLOCK (RTC) RESET CONTROL (RCU) POWER MANAGEMENT (DPM) DEBUG UNIT ARM® CoreSightTM WATCHPOINTS (SWU) CORE 0 L1 CACHE 32 kB L1 I-CACHE 32 kB L1 D-CACHE L2 CACHE 256 kB (PARITY) CORE 1 S L1 SRAM (PARITY) 5M BITS (640 kB) SRAM/CACHE CORE 2 S L1 SRAM (PARITY) 5M BITS (640 kB) SRAM/CACHE SYSTEM CROSSBAR AND DMA SUBSYSTEM L3 MEMORY INTERFACES DDR3 DDR2 LPDDR1 DDR3 DDR2 LPDDR1 16 DATA 16 DATA SYSTEM L2 MEMORY 2M BITS (256 kB) L2 SRAM (ECC) 4M BITS (512 kB) 2 × 2M BITS ROM SYSTEM ACCELERATION DSP FUNCTIONS (FFT/iFFT, FIR, IIR, HAE/SINC) ENCRYPTION/DECRYPTION Figure 1. Processor Block Diagram PERIPHERALS SRU 4× PRECISION CLOCK GENERATORS ASRC FULL SPORT 8× PAIRS 0-7 2x DAI 2x PIN BUFFER 2× S/PDIF Rx/Tx 3× I2C 2× LINK PORTS 2× SPI + 1× QUAD SPI 3× UARTs 1× EPPI 3× ePWM 8× TIMERS + 1× COUNTER ADC CONTROL MODULE (ACM) ASYNC MEMORY (16-BIT) 2× CAN2.0 SD/SDIO/eMMC G P I O MLB 3-PIN 2× EMAC SINC FILTER 8x SHARC FLAGS 2× USB 2.0 HS MLB 6-PIN PCIe2.0 (1 lane) HADC (8 CHAN, 12-BIT) Rev. PrF Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 ARM CORTEX-A5 PROCESSOR The ARM Cortex-A5 processor (Figure 2) is a high performance processor with the following features: • Instruction and Data L1 cache units (32/32K bytes) • In-order pipeline with dynamic branch prediction • ARM, Thumb, and ThumbEE instruction set support • TrustZone security extensions • Harvard level 1 memory system with a memory manage- ment unit (MMU) • ARM v7 debug architecture • Trace support through an embedded trace macrocell (ETM) interface • Extension: vector floating-point unit (IEEE754) with trap- less execution • Extension: media processing engine (MPE) with NEON technology • Extension: Jazelle hardware acceleration EMBEDDED TRACE MACROCELL (ETM) INTERFACE CoreSight INTERFACE DEBUG CP15 NEONTM MEDIA PROCESSING ENGINE CORTEX-A5 PROCESSOR DATA PROCESSING UNIT (DPU) DATA MICRO-TLB PREFETCH UNIT AND BRANCH PREDICTOR (PFU) INSTRUCTION MICRO-TLB DATA STORE BUFFER (STB) DATA CACHE UNIT (DCU) 32 KB MAIN TRANSMISSION LOOKINSIDE BUFFER (TLB) INSTRUCTION CACHE UNIT (ICU) 32 KB BUS INTERFACE UNIT (BIU) A5 BUS MASTER PORT GENERIC INTERRUPT CONTROLLER (PrimeCell® PL-390) L2 CACHE CONTROLLER (CoreLinkTM PL-310) 256 KB DATA MASTER PORTS SHARC PROCESSORS SYSTEM FABRIC Figure 2. ARM Cortex A-5 Processor Block Diagram TO OTHER CORES Rev. PrF \| Page 5 of 168 \| February 2016 5 Page Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 SYSTEM MEMORY MAP Table 4. L1 Block 0, 1, 2, and 3 SHARC Addressing Memory Map (Private Address Space) Memory L1 Block 0 SRAM (1.5 Mb) L1 Block 1 SRAM (1.5 Mb) L1 Block 2 SRAM (1 Mb) L1 Block 3 SRAM (1 Mb) Long Word (64 Bits) 0x00048000– 0x0004DFFF 0x00058000– 0x0005DFFF 0x00060000– 0x00063FFF 0x00070000– 0x00073FFF Extended Precision/ ISA Code (48 Bits) 0x00090000– 0x00097FFF 0x000B0000– 0x000B7FFF 0x000C0000– 0x000C5554 0x000E0000– 0x000E5554 Normal Word (32 Bits) 0x00090000– 0x0009BFFF 0x000B0000– 0x000BBFFF 0x000C0000– 0x000C7FFF 0x000E0000– 0x000E7FFF Short Word/ VISA Code (16 Bits) 0x00120000– 0x00137FFF 0x00160000– 0x00177FFF 0x00180000– 0x0018FFFF 0x001C0000– 0x001CFFFF Byte Access (8 Bits) 0x00240000– 0x0026FFFF 0x002C0000– 0x002EFFFF 0x00300000– 0x0031FFFF 0x00380000– 0x0039FFFF Table 5. L2 Memory Addressing Map Memory Byte Address Space ARM – Data Access and Instruction Fetch SHARC – Data Access Normal Word Address Space for Data Access SHARC ARM: 0x00000000–0x00007FFF L2 Boot-ROM01 SHARC/DMA: 0x20000000–0x20007FFF 0x08000000–0x08001FFF L2 RAM (2 Mb) 0x20080000–0x200BFFFF 0x08020000–0x0802FFFF Boot ROM1 0x20100000–0x20107FFF 0x08040000–0x08041FFF L2 ROM1 0x20180000–0x201BFFFF 0x08060000–0x0806FFFF Boot ROM2 0x20200000–0x20207FFF 0x08080000–0x08081FFF L2 ROM2 0x20280000–0x202BFFFF 0x080A0000–0x080AFFFF 1 From the ARM point of view, L2 Boot-ROM0 byte address space is 0x 0000 0000–0x 0000 7FFF. Instruction Fetch VISA Address Space SHARC Instruction Fetch ISA Address Space SHARC 0x00B80000–0x00B83FFF 0x00580000–0x00581555 0x00BA0000–0x00BBFFFF 0x005A0000–0x005AAAAF 0x00B00000–0x00B03FFF 0x00500000–0x00501555 0x00B20000–0x00B3FFFF 0x00520000–0x0052AAAF 0x00B40000–0x00B43FFF 0x00540000–0x00541555 0x00B60000–0x00B7FFFF 0x00560000–0x0056AAAF Table 6. SHARC L1 Memory in Multiprocessor Space L1 Memory of SHARC1 in Multiprocessor Space L1 Memory of SHARC2 in Multiprocessor Space Address via Slave1 Port Address via Slave2 Port Address via Slave1 Port Address via Slave2 Port Memory Block Block0 Block1 Block2 Block3 Block0 Block1 Block2 Block3 Block0 Block1 Block2 Block3 Block0 Block1 Block2 Block3 Byte Address Space for ARM and SHARC 0x28240000–0x28270000 0x282C0000–0x282F0000 0x28300000–0x28320000 0x28380000–0x283A0000 0x28640000–0x28670000 0x286C0000–0x286F0000 0x28700000–0x28720000 0x28780000–0x287A0000 0x28A40000–0x28A70000 0x28AC0000–0x28AF0000 0x28B00000–0x28B20000 0x28B80000–0x28BA0000 0x28E40000–0x28E70000 0x28EC0000–0x28EF0000 0x28F00000–0x28F20000 0x28F80000–0x28FA0000 Normal Word Address Space for SHARC 0x0A090000–0x0A09C000 0x0A0B0000–0x0A0BC000 0x0A0C0000–0x0A0C8000 0x0A0E0000–0x0A0E8000 0x0A190000–0x0A19C000 0x0A1B0000–0x0A1BC000 0x0A1C0000–0x0A1C8000 0x0A1E0000–0x0A1E8000 0x0A290000–0x0A29C000 0x0A2B0000–0x0A2BC000 0x0A2C0000–0x0A2C8000 0x0A2E0000–0x0A2E8000 0x0A390000–0x0A39C000 0x0A3B0000–0x0A3BC000 0x0A3C0000–0x0A3C8000 0x0A3E0000–0x0A3E8000 Rev. PrF \| Page 11 of 168 \| February 2016 11 Page

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