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PDF ADN2917 Data sheet ( Hoja de datos )
| Número de pieza | ADN2917 | |
| Descripción | Continuous Rate 8.5 Gbps to 11.3 Gbps Clock and Data Recovery IC | |
| Fabricantes | Analog Devices | |
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Data Sheet
Continuous Rate 8.5 Gbps to 11.3 Gbps Clock and
Data Recovery IC with Integrated Limiting Amp/EQ
ADN2917
FEATURES
GENERAL DESCRIPTION
Serial data input: 8.5 Gbps to 11.3 Gbps
No reference clock required
Exceeds SONET/SDH requirements for jitter
transfer/generation/tolerance
Quantizer sensitivity: 9.2 mV p-p typical
(limiting amplifier mode)
Optional limiting amplifier and equalizer inputs
Programmable jitter transfer bandwidth to support G.8251 OTN
Programmable slice level
Sample phase adjust
Output polarity invert
Programmable LOS threshold via I2C
I2C to access optional features
LOS alarm (limiting amplifier mode only)
LOL indicator
PRBS generator/detector
Application-aware power
352 mW at 8.5 Gbps, equalizer mode, no clock output
430 mW at 11.3 Gbps, equalizer mode, no clock output
Power supplies: 1.2 V, flexible 1.8 V to 3.3 V, and 3.3 V
4 mm × 4 mm 24-lead LFCSP
APPLICATIONS
SONET/SDH OC-192, 10GFC, and 10GE and all associated FECs
XFP, line cards, clocks, routers, repeaters, instruments
Any rate regenerators/repeaters
The ADN2917 provides the receiver functions of quantization,
signal level detect, and clock and data recovery for continuous data
rates from 8.5 Gbps to 11.3 Gbps. The ADN2917 automatically
locks to all data rates without the need for an external reference
clock or programming. ADN2917 jitter performance exceeds all
jitter specifications required by SONET/SDH, including jitter
transfer, jitter generation, and jitter tolerance.
The ADN2917 provides manual or automatic slice adjust and
manual sample phase adjusts. Additionally, the user can select a
limiting amplifier or equalizer at the input. The equalizer is
either adaptive or can be manually set.
The receiver front-end loss of signal (LOS) detector circuit
indicates when the input signal level has fallen below a user-
programmable threshold. The LOS detect circuit has hysteresis
to prevent chatter at the LOS output. In addition, the input
signal strength can be read through the I2C registers.
The ADN2917 also supports pseudorandom binary sequence
(PRBS) generation, bit error detection, and input data rate
readback features.
The ADN2917 is available in a compact 4 mm × 4 mm, 24-lead
frame chip scale package (LFCSP). All ADN2917 specifications
are defined over the ambient temperature range of −40°C to +85°C,
unless otherwise noted.
SCK
SDA
FUNCTIONAL BLOCK DIAGRAM
LOL
REFCLKP/
REFCLKN
(OPTIONAL)
DATOUTP/
DATOUTN
CLKOUTP/
CLKOUTN
I2C_ADDR
I2C REGISTERS
FREQUENCY
ACQUISITION
AND LOCK
DETECTOR
DATA RATE
ADN2917
CML
CLK
DDR
CML
LOS
LOS
DETECT
PIN
NIN
50Ω
2
50Ω
I2C
VCM
VCC
FLOAT
LA
BYPASS
EQ
I2C
SAMPLE
PHASE
ADJUST
DATA
INPUT
SAMPLER
FIFO
RXD
RXCK
DOWNSAMPLER
AND LOOP
FILTER
PHASE
SHIFTER
÷N
DCO
CLOCK
÷2
Figure 1.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADN2917
Parameter
8GFC,3 JTSPAT
Sinusoidal Jitter at 340 kHz
Sinusoidal Jitter at 5.098 MHz
Sinusoidal Jitter at 80 MHz
Rx Jitter Tracking Test4
510 kHz, 1 UI
100 kHz, 5 UI
Test Conditions/Comments
Voltage modulation amplitude (VMA) = 170 mV p-p at
100 MHz, 425 mV p-p at 100 MHz, 170 mV p-p at 2.5 GHz,
and 425 mV p-p at 2.5 GHz excitation frequency5
Min Typ
6.7
0.53
0.59
10−12
10−12
<10−12
<10−12
Max
Unit
UI p-p
UI p-p
UI p-p
BER
BER
1 Jitter transfer bandwidth is programmable by adjusting TRANBW[2:0] in the DPLLA register (Register 0x10).
2 Set TRANBW[2:0] (Bits[D2:D0] in Register 0x10) = 1 to enter OTN mode. OTN is the optical transport network as defined in ITU G.709.
3 Fibre Channel Physical Interface 4 standard, FC-PI-4, Rev 8.00, May 21, 2008.
4 Conditions of FC-PI-4, Rev 8.00, Table 27, 800-DF-EL-S apply.
5 Must have zero errors during the tests for an interval of time that is ≤10−12 BER to pass the tests.
OUTPUT AND TIMING SPECIFICATIONS
TA = TMIN to TMAX, VCC = VCCMIN to VCCMAX, VCC1 = VCC1MIN to VCC1MAX, VDD = VDDMIN to VDDMAX, VEE = 0 V, input data
pattern: PRBS 223 − 1, ac-coupled to 100 Ω differential termination load, I2C register default settings, unless otherwise noted.
Table 3.
Parameter
CML OUTPUT CHARACTERISTICS
Data Differential Output Swing
Clock Differential Output Swing
Data Differential Output Swing
Clock Differential Output Swing
Output High Voltage
Output Low Voltage
CML OUTPUT TIMING CHARACTERISTICS
Rise Time
Fall Time
Setup Time, Full Rate Clock
Hold Time, Full Rate Clock
Setup Time, DDR Clock
Hold Time, DDR clock
Test Conditions/Comments
Min
OC-192, DATA_SWING[3:0] (Bits[D7:D4] in
Register 0x1F) setting = 0xC (default)
OC-192, DATA_SWING[3:0] setting = 0xF (maximum)
OC-192, DATA_SWING[3:0] setting = 0x4 (minimum)
OC-192, CLOCK_SWING[3:0] (Bits[D3:D0] in
Register 0x1F) setting = 0xC (default)
OC-192, CLOCK_SWING[3:0] setting = 0xF (maximum)
OC-192, CLOCK_SWING[3:0] setting = 0x4 (minimum)
8GFC, DATA_SWING[3:0] setting = 0xC (default)
8GFC, DATA_SWING[3:0] setting = 0xF (maximum)
8GFC, DATA_SWING[3:0] setting = 0x4 (minimum
8GFC, CLOCK_SWING[3:0] setting = 0xC (default)
8GFC, CLOCK_SWING[3:0] setting = 0xF (maximum)
8GFC, CLOCK_SWING[3:0] setting = 0x4 (minimum)
VOH, dc-coupled
535
668
189
406
448
162
540
662
190
426
489
166
VCC – 0.05
VOL, dc-coupled
VCC – 0.36
20% to 80%, at OC-192, DATOUTN/DATOUTP
20% to 80%, at OC-192, CLKOUTN/CLKOUTP
20% to 80%, at 8GFC,1 DATOUTN/DATOUTP
20% to 80%, at 8GFC,1 CLKOUTN/CLKOUTP
80% to 20%, at OC-192, DATOUTN/DATOUTP
80% to 20%, at OC-192, CLKOUTN/CLKOUTP
80% to 20%, at 8GFC,1 DATOUTN/DATOUTP
80% to 20%, at 8GFC,1 CLKOUTN/CLKOUTP
tS (see Figure 2)
tH (see Figure 2)
tS (see Figure 3)
tH (see Figure 3)
17.4
22.2
20.4
23.1
17.5
23.9
23
25
Typ
600
724
219
508
583
217
600
725
214
518
603
213
VCC −
0.025
VCC −
0.325
32.6
28.3
33.1
29.7
33
29.2
34.2
31.3
0.5
0.5
0.5
0.5
Max Unit
672 mV p-p
771 mV p-p
252 mV p-p
570 mV p-p
659 mV p-p
249 mV p-p
666 mV p-p
778 mV p-p
245 mV p-p
588 mV p-p
680 mV p-p
245 mV p-p
VCC V
VCC − V
0.29
46.5 ps
33.1 ps
44 ps
35.8 ps
49.1 ps
33.7 ps
46.8 ps
37.1 ps
UI
UI
UI
UI
Rev. A | Page 5 of 32
5 Page 
Data Sheet
0.6
0.5
0.4
0.3
0.2 TYPICAL
ADAPTIVE EQ
SETTING
0.1
0
0 2 4 6 8 10 12 14 16
EQ SETTING
Figure 10. BER in Equalizer Mode vs. EQ Compensation at OC-192
(Measured with an OC-192 Signal of 400 mV p-p diff, on 15 Inch FR4 Traces,
with Variant EQ Compensation, Including Adaptive EQ)
12
10
8
6
4
2
0
DATA RATE (Gbps)
Figure 11. Sensitivities of SONET/SDH Data Rates (BER = 10−10)
ADN2917
16
14
12
10
8
6
4
2
0
DATA RATE (Gbps)
Figure 12. Sensitivities of Non SONET/SDH Data Rates (BER = 10−12)
Rev. A | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADN2917.PDF ] | |
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