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ADL5202 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADL5202
Beschreibung Digitally Controlled VGA
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADL5202 Datasheet, Funktion
Data Sheet
Wide Dynamic Range, High Speed,
Digitally Controlled VGA
ADL5202
FEATURES
Dual independent, digitally controlled VGAs
−11.5 dB to +20 dB gain range
0.5 dB ± 0.1 dB step size
150 Ω differential input and output
7.5 dB noise figure at maximum gain
OIP3 > 50 dBm at 200 MHz
−3 dB upper frequency bandwidth of 700 MHz
Multiple control interface options
Parallel 6-bit control interface (with latch)
Serial peripheral interface (SPI) (with fast attack)
Gain up/down mode
Wide input dynamic range
Low power mode option
Power-down control
Single 5 V supply operation
40-lead, 6 mm × 6 mm LFCSP package
APPLICATIONS
Differential ADC drivers
High IF sampling receivers
High output power IF amplification
Instrumentation
GENERAL DESCRIPTION
The ADL5202 is a digitally controlled, variable gain, wide band-
width amplifier that provides precise gain control, high output
IP3, and low noise figure. The excellent distortion performance
and high signal bandwidth make the ADL5202 an excellent gain
control device for a variety of receiver applications. The
ADL5202 also incorporates a low power mode option that
lowers the supply current.
For wide input dynamic range applications, the ADL5202
provides a broad 31.5 dB gain range with 0.5 dB resolution. The
gain is adjustable through multiple gain control interface options:
parallel, serial peripheral interface, and up/down.
Incorporating proprietary distortion cancellation techniques,
the ADL5202 achieves a better than 50 dBm output IP3 at
frequencies approaching 200 MHz for most gain settings.
FUNCTIONAL BLOCK DIAGRAM
SIDE A
SPI WITH FA,
PARALLEL WITH LATCH,
UP/DN
PWUPA
VPOS
LOGIC
VINA+
VINA–
MODE0,
MODE1
PM
1500dB TO 31.5dB
CONTROL
CIRCUITRY
VINB+
VINB–
1500dB TO 31.5dB
LOGIC
+20dB
150
VOUTA+
VOUTA–
+20dB
150
VOUTB+
VOUTB–
ADL5202
SIDE B
SPI WITH FA,
PARALLEL WITH LATCH,
UP/DN
PWUPB
Figure 1.
GND
The ADL5202 is powered on by applying the appropriate logic
level to the PWUPx pins. The quiescent current of the ADL5202
is typically 160 mA in low power mode. When configured in high
performance mode for more demanding applications, the quiescent
current is 210 mA. When powered down, the ADL5202 consumes
less than 14 mA and offers excellent input-to-output isolation.
The gain setting is preserved during power-down.
Fabricated on an Analog Devices, Inc., high speed SiGe process,
the ADL5202 provides precise gain adjustment capabilities with
good distortion performance and low phase error. The ADL5202
amplifier comes in a compact, thermally enhanced 40-lead,
6 mm × 6 mm LFCSP package and operates over a temperature
range of −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.






ADL5202 Datasheet, Funktion
ADL5202
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
CSA/A3 1
A4 2
A5 3
MODE1 4
MODE0 5
PM 6
GND 7
SIDO/B5 8
SCLK/B4
GS1/CSB/B3
9
10
PIN 1
INDICATOR
ADL5202
TOP VIEW
(Not to Scale)
EXPOSED
PADDLE
30 VOUTA–
29 VOUTA+
28 VPOS
27 VPOS
26 VPOS
25 VPOS
24 VPOS
23 VPOS
22 VOUTB+
21 VOUTB–
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE (EP) MUST BE CONNECTED TO
A LOW IMPEDANCE GROUND PAD.
Figure 5. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 CSA/A3 Channel A Select (CSA). When serial mode is enabled, a logic low (0 V ≤ CSA ≤ 0.8 V) selects Channel A.
Bit 3 for Channel A Parallel Gain Control Interface (A3).
2 A4
Bit 4 for Channel A Parallel Gain Control Interface.
3 A5
Bit 5 (MSB) for Channel A Parallel Gain Control Interface.
4 MODE1 MSB for Mode Control. With the MODE0 pin, selects parallel, SPI, or up/down interface mode.
5 MODE0 LSB for Mode Control. With the MODE1 pin, selects parallel, SPI, or up/down interface mode.
6 PM
Performance Mode. A logic low (0 V ≤ PM ≤ 0.8 V) enables high performance mode. A logic high
(1.4 V ≤ PM ≤ 3.3 V) enables low power mode.
7, 18, 33, EP GND
Ground. The exposed paddle (EP) must be connected to a low impedance ground pad.
8
SDIO/B5
Serial Data Input/Output (SDIO). When CSA or CSB is pulled low, SDIO is used for reading and writing
to the SPI port.
Bit 5 for Channel B Parallel Gain Control Interface (B5).
9
SCLK/B4
Serial Clock Input in SPI Mode (SCLK).
Bit 4 for Channel B Parallel Gain Control Interface (B4).
10
GS1/CSB/B3
MSB for Gain Step Size Control in Up/Down Mode (GS1).
Channel B Select (CSB). When serial mode is enabled, a logic low (0 V ≤ CSB≤ 0.8 V) selects Channel B.
Bit 3 for Channel B Parallel Gain Control Interface (B3).
11
GS0/FA_B/B2
LSB for Gain Step Size Control in Up/Down Mode (GS0).
Fast Attack (FA_B). In serial mode, a logic high (1.4 V ≤ FA_B ≤ 3.3 V) attenuates Channel B according to
the FA setting in the SPI word.
Bit 2 for Channel B Parallel Gain Control Interface (B2).
12 UPDN_CLK_B/B1 Clock Interface for Channel B Up/Down Function (UPDN_CLK_B).
Bit 1 for Channel B Parallel Gain Control Interface (B1).
13 UPDN_DAT_B/B0 Data Pin for Channel B Up/Down Function (UPDN_DAT_B).
Bit 0 for Channel B Parallel Gain Control Interface (B0).
14 LATCHB
Channel B Latch. A logic low (0 V ≤ LATCHB ≤ 0.8 V) allows gain changes on Channel B. A logic high
(1.4 V ≤ LATCHB ≤ 3.3 V) prevents gain changes on Channel B.
Rev. 0 | Page 6 of 32

6 Page









ADL5202 pdf, datenblatt
ADL5202
–50 –11.5dB
–60
0dB
10dB
20dB
–70
–20
–30
–40
–80 –50
–90 –60
–100
–70
–110
–80
–120
–90
–130
–100
–140
–110
–150
0
–120
50 100 150 200 250 300 350
FREQUENCY (MHz)
Figure 30. Harmonic Distortion vs. Frequency at Four Gain Codes,
Low Power Mode
–50
TA = –40°C
–60 TA = +25°C
TA = +85°C
–70
–20
–30
–40
–80 –50
–90 –60
–100
–70
–110
–80
–120
–90
–130
–100
–140
–150
0
–110
–120
50 100 150 200 250 300 350
FREQUENCY (MHz)
Figure 31. Harmonic Distortion vs. Frequency, Three Temperatures,
Low Power Mode
Data Sheet
–60
–11.5dB
0dB
–70 10dB
20dB
–80
–40
–50
–60
–90 –70
–100
–80
–110
–90
–120
–100
–130
–110
–140
–120
–6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6
POUT (dBm)
Figure 33. Harmonic Distortion vs. Power at Four Gain Codes,
Frequency = 140 MHz, Low Power Mode
–70
TA = –40°C
TA = +25°C
–80 TA = +85°C
–50
–60
–90 –70
–100
–80
–110
–90
–120
–100
–130
–110
–6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6
POUT (dBm)
Figure 34. Harmonic Distortion vs. Power, Frequency = 140 MHz, Three
Temperatures, Low Power Mode
1
4
CH1 200mV
CH4 1mV
M 10ns 10GS/s A CH4
IT 4ps/pt
Figure 32. Enable Time Domain Response
1.12V
CH1 200mV/DIV
CH4 1V/DIV
TIME (10ns/DIV)
Figure 35. Disable Time Domain Response
Rev. 0 | Page 12 of 32

12 Page





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