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WM8734 Schematic ( PDF Datasheet ) - Wolfson Microelectronics

Teilenummer WM8734
Beschreibung Stereo Audio CODEC
Hersteller Wolfson Microelectronics
Logo Wolfson Microelectronics Logo 




Gesamt 30 Seiten
WM8734 Datasheet, Funktion
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Stereo Audio CODEC
WM8734
DESCRIPTION
The WM8734 is a low power stereo CODEC ideal for
DVD/RW, MP3, media centre and automotive applications
Stereo line inputs are provided, along with a mute function
and programmable line level volume control.
Stereo 24-bit multi-bit sigma delta ADCs and DACs are used
with oversampling digital interpolation and decimation filters.
Digital audio input word lengths from 16-32 bits and
sampling rates from 8kHz to 96kHz are supported.
Stereo audio line level outputs are provided along with anti-
thump mute and power up/down circuitry.
The device is controlled via a 2 or 3 wire serial interface.
The interface provides access to all features including level
controls, mutes, de-emphasis and power management
facilities. The device is available in a 20-lead SSOP
package.
FEATURES
Audio Performance
90dB SNR (‘A’ weighted @ 48kHz) ADC
100dB SNR (‘A’ weighted @ 48kHz) DAC
2.7 – 3.6V Digital Supply Operation
2.7 – 3.6V Analogue Supply Operation
ADC and DAC Sampling Frequency: 8kHz – 96kHz
Selectable ADC High Pass Filter
2 or 3-Wire MPU Serial Control Interface
Programmable Audio Data Interface Modes
I2S, Left, Right Justified or DSP
16/20/24/32 bit Word Lengths
Master or Slave Clocking Mode
Stereo Audio Inputs and Outputs
20-lead SSOP Package
APPLICATIONS
CD and Minidisc Recorder
MP3 Player / Recorder
BLOCK DIAGRAM
AVDD
VMID
AGND
RLINEIN
LLINEIN
CONTROL INTERFACE
W
WM8734
VOL
+12 to -34.5dB,
1.5dB Steps
VOL
+12 to -34.5dB,
1.5dB Steps
CLKIN
DIVIDER
(Div x1, x2)
ADC
ADC
DIGITAL
FILTERS
DAC
MUTE
DAC
MUTE
DIGTAL AUDIO INTERFACE
ROUT
LOUT
WOLFSON MICROELECTRONICS plc
Production Data, August 2013, Rev 4.4
Copyright 2013 Wolfson Microelectronics plc






WM8734 Datasheet, Funktion
WM8734
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
0.3 x DBVDD
V
Input HIGH level
VIH
0.7 x DBVDD
V
Output LOW
VOL
0.10 x
DBVDD
V
Output HIGH
VOH
0.9 x DBVDD
V
Power On Reset Threshold (DCVDD)
DCVDD Threshold On -> Off
Vth
0.9 V
Hysteresis
VIH
0.3 V
DCVDD Threshold Off -> On
Analogue Reference Levels
VOL
0.6 V
Reference voltage
VVMID
AVDD/2
V
Potential divider resistance
RVMID
50k
Line Input to ADC
Input Signal Level (0dB)
VINLINE
1.0
AVDD/3.3
Vrms
Signal to Noise Ratio
(Note 1,2,3)
SNR
A-weighted, 0dB gain
@ fs = 48kHz
A-weighted, 0dB gain
@ fs = 96kHz
85
90
90
dB
A-weighted, 0dB gain
@ fs = 48kHz,
88
AVDD = 2.7V
Dynamic Range (Note 3)
DNR
A-weighted, -60dB full
scale input
85
90
dB
Total Harmonic Distortion
THD
-1dB input, 0dB gain
-84 -74 dB
Power Supply Rejection Ratio
PSSR
1kHz 100mVpp
50
dB
20Hz to 20kHz
100mVpp
45
ADC channel separation
1kHz input
90 dB
Programmable Gain
1kHz input
-34.5
0
+12 dB
Rsource < 50
Programmable Gain Step Size
Guaranteed Monotonic
1.5
dB
Mute attenuation
0dB, 1kHz input
80
dB
Input Resistance
RINLINE
0dB gain
20k 30k
12dB gain
10k 15k
Input Capacitance
CINLINE
10 pF
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PD, Rev 4.4, August 2013
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6 Page









WM8734 pdf, datenblatt
WM8734
MPU INTERFACE TIMING
Production Data
CSB
SCLK
tCSL
tSCY
tSCH
tSCL
tCSH
tSCS
tCSS
SDIN
tDSU
tDHO
LSB
Figure 6 Program Register Input Timing – 3-Wire MPU Serial Control Mode
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
Program Register Input Information
SCLK rising edge to CSB rising
edge
tSCS
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
tSCY
tSCL
tSCH
tDSU
SCLK to SDIN hold time
CSB pulse width low
CSB pulse width high
tDHO
tCSL
tCSH
CSB rising to SCLK rising
tCSS
TEST CONDITIONS
MIN TYP MAX UNIT
60 ns
80 ns
20 ns
20 ns
20 ns
20 ns
20 ns
20 ns
20 ns
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PD, Rev 4.4, August 2013
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12 Page





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