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WM8750JL Schematic ( PDF Datasheet ) - Wolfson Microelectronics

Teilenummer WM8750JL
Beschreibung Stereo CODEC
Hersteller Wolfson Microelectronics
Logo Wolfson Microelectronics Logo 




Gesamt 30 Seiten
WM8750JL Datasheet, Funktion
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WM8750JL
Stereo CODEC for Portable Audio Applications
DESCRIPTION
The WM8750JL is a low power, high quality stereo CODEC
designed for portable digital audio applications.
The device integrates complete interfaces to stereo or mono
microphones and a stereo headphone. External component
requirements are drastically reduced as no separate
microphone or headphone amplifiers are required.
Advanced on-chip digital signal processing performs graphic
equaliser, 3-D sound enhancement and automatic level
control for the microphone or line input.
The WM8750JL can operate as a master or a slave, with
various master clock frequencies including 12 or 24MHz for
USB devices, or standard 256fs rates like 12.288MHz and
24.576MHz. Different audio sample rates such as 96kHz,
48kHz, 44.1kHz are generated directly from the master
clock without the need for an external PLL.
The WM8750JL operates at supply voltages down to 1.8V,
although the digital core can operate at voltages down to
1.42V to save power, and the maximum for all supplies is
3.6 Volts. Different sections of the chip can also be powered
down under software control.
The WM8750JL is supplied in a very small and thin 5x5mm
QFN package, ideal for use in hand-held and portable
systems.
BLOCK DIAGRAM
FEATURES
DAC SNR 97dB (‘A’ weighted), THD -85dB at 48kHz, 3.3V
ADC SNR 88dB (‘A’ weighted), THD -80dB at 48kHz, 3.3V
Complete Stereo / Mono Microphone Interface
- Programmable ALC (timed out) / Noise Gate
On-chip 400mW BTL Speaker Driver (mono)
On-chip Headphone Driver
- >40mW output power on 16/ 3.3V
- THD –73dB at 5mW, SNR 98dB with 16load
- No DC blocking capacitors required (capless mode)
Separately mixed mono output
Digital Graphic Equaliser
Low Power
- 6 mW stereo playback (1.8V / 1.5V supplies)
- 13 mW record & playback (1.8V / 1.5V supplies)
Low Supply Voltages
- Analogue 1.8V to 3.6V
- Digital core: 1.42V to 3.6V
- Digital I/O: 1.8V to 3.6V
256fs / 384fs or USB master clock rates: 12MHz, 24MHz
Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48,
88.2, 96kHz generated internally from master clock
5x5x0.9mm QFN package
APPLICATIONS
Portable Media Player
Mobile phone handsets
Mobile gaming
WOLFSON MICROELECTRONICS plc
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Production Data, April 2012, Rev 4.1
Copyright 2012 Wolfson Microelectronics plc






WM8750JL Datasheet, Funktion
WM8750JL
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions
DCVDD = 1.5V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, ADCOSR=1, DACOSR=1,
PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP
Analogue Inputs (LINPUT1, RINPUT1, LINPUT2, RINPUT2, LINPUT3, RINPUT3) to ADC out
Full Scale Input Signal Level
(for ADC 0dB Input at 0dB Gain)
VINFS
AVDD/3.3
Input Resistance
PGA gain=0dB into ADC
22
Pins LINPUT1/2/3, RINPUT1/2/3
PGA gain=+30dB into
ADC
1.5
DC Measurement from
L/RINPUT1
16
MAX
UNIT
V rms
k
input pin unused
17
Input Capacitance
10 pF
Signal to Noise Ratio
SNR
AVDD = 3.3V
80 88
dB
(A-weighted)
ADCOSR=1
AVDD = 3.3V
95
ADCOSR=0
AVDD = 1.8V
85
ADCOSR=1
AVDD = 1.8V
90
ADCOSR=0
Total Harmonic Distortion
THD
-1dBFs input,
-80 dB
AVDD = 3.3V
0.01 %
-1dBFs input,
-74
AVDD = 1.8V
0.02
ADC Channel Separation
1kHz signal
85 dB
Channel Matching
1kHz signal
-0.5
0.5 dB
Analogue Outputs (LOUT1/2, ROUT1/2, MONOOUT)
0dB Full scale output voltage
AVDD/3.3
Vrms
Mute attenuation
1kHz, full scale signal
90
dB
MONOOUT pin
81
Channel Separation
analogue in
85 dB
to analogue out
DAC to Line-Out (L/ROUT2 with 10k/ 50pF load)
Signal to Noise Ratio
SNR
AVDD=3.3V
90 97
dB
(A-weighted)
AVDD=1.8V
94
Total Harmonic Distortion
THD
AVDD=3.3V
-85 dB
AVDD=1.8V
-79
Channel Separation
1kHz signal
100 dB
Headphone Output (LOUT1/ROUT1, using capacitors)
Output Power per channel
Total Harmonic Distortion plus
Noise
PO
THD+N
Output power is very closely correlated with THD; see below.
HPVDD=1.8V, RL=32
0.02
PO=5mW
-73
%
dB
HPVDD=1.8V, RL=16
PO=5mW
0.03
-70
HPVDD=3.3V, RL=32,
PO=5mW
0.015
-76
HPVDD=3.3V, RL=16,
PO=5mW
0.02
-73
Signal to Noise Ratio
SNR
HPVDD = 3.3V
90
98
dB
(A-weighted)
HPVDD = 1.8V
93
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PD, April 2012, Rev 4.1
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WM8750JL pdf, datenblatt
WM8750JL
Production Data
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Bit Clock Timing Information
BCLK rise time (10pF load)
tBCLKR
3 ns
BCLK fall time (10pF load)
tBCLKF
3 ns
BCLK duty cycle (normal mode, BCLK = MCLK/n)
BCLK duty cycle (USB mode, BCLK = MCLK)
tBCLKDS
tBCLKDS
50:50
TMCLKDS
Audio Data Input Timing Information
ADCLRC/DACLRC propagation delay from BCLK falling edge
tDL
10 ns
ADCDAT propagation delay from BCLK falling edge
tDDA
40 ns
DACDAT setup time to BCLK rising edge
tDST 10
ns
DACDAT hold time from BCLK rising edge
tDHT 10
ns
AUDIO INTERFACE TIMING – SLAVE MODE
BCLK
tBCH
tBCL
tBCY
DACLRC/
ADCLRC
DACDAT
tDS
tDD
ADCDAT
tLRH
tDH
tLRSU
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY 50
ns
BCLK pulse width high
tBCH 20
ns
BCLK pulse width low
tBCL 20
ns
ADCLRC/DACLRC set-up time to BCLK rising edge
tLRSU
10
ns
ADCLRC/DACLRC hold time from BCLK rising edge
tLRH 10
ns
DACDAT hold time from BCLK rising edge
tDH 10
ns
ADCDAT propagation delay from BCLK falling edge
tDD
10 ns
Note:
BCLK period should always be greater than or equal to MCLK period.
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PD, April 2012, Rev 4.1
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