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PDF WM8918 Data sheet ( Hoja de datos )
| Número de pieza | WM8918 | |
| Descripción | Ultra Low Power DAC | |
| Fabricantes | Wolfson Microelectronics | |
| Logotipo |  |
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WM8918
Ultra Low Power DAC for Portable Audio Applications
DESCRIPTION
The WM8918 is a high performance ultra-low power stereo
DAC optimised for portable audio applications.
The device features stereo ground-referenced headphone
amplifiers using the Wolfson ‘Class-W’ amplifier techniques -
incorporating an innovative dual-mode charge pump
architecture - to optimise efficiency and power consumption
during playback. The ground-referenced headphone and line
outputs eliminate AC coupling capacitors, and both outputs
include common mode feedback paths to reject ground
noise.
Control sequences for audio path setup can be pre-loaded
and executed by an integrated control write sequencer to
reduce software driver development and minimise pops and
clicks via Wolfson’s SilentSwitch™ technology.
The analogue input stage can be configured for single
ended or differential inputs. Up to 3 stereo microphone or
line inputs may be connected. The input impedance is
constant with PGA gain setting.
A stereo digital microphone interface is provided, with a
choice of two inputs. The analogue or digital microphone
inputs can be mixed into the headphone or line output paths.
A dynamic range controller provides compression and level
control to support a wide range of portable recording
applications in conjunction with the digital microphone
interface. Anti-clip and quick release features offer good
performance in the presence of loud impulsive noises.
ReTuneTM Mobile 5-band parametric equaliser with fully
programmable coefficients is integrated for optimization of
speaker characteristics. Programmable dynamic range
control is also available for maximizing loudness, protecting
speakers from clipping and preventing premature shutdown
due to battery droop.
Common audio sampling frequencies are supported from a
wide range of external clocks, either directly or generated
via the FLL.
The WM8918 can operate directly from a single 1.8V
switched supply. For optimal power consumption, the digital
core can be operated from a 1.0V supply.
FEATURES
3.8mW quiescent power consumption for DAC to
headphone playback
DAC SNR 96dB typical, THD -86dB typical
2.4mW quiescent power consumption for analogue bypass
playback
Control write sequencer for pop minimised start-up and
shutdown
Single register write for default start-up sequence
Integrated FLL provides all necessary clocks
- Self-clocking modes allow processor to sleep
- All standard sample rates from 8kHz to 96kHz
Stereo digital microphone input
3 single ended inputs per stereo channel
1 fully differential mic / line input per stereo channel
Digital Dynamic Range Controller (compressor / limiter)
Digital sidetone mixing
Ground-referenced headphone driver
Ground-referenced line outputs
32-pin QFN package (4x4mm, 0.4mm pitch)
APPLICATIONS
Wireless headsets
Portable multimedia players
Handheld gaming
WOLFSON MICROELECTRONICS plc
To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews
Production Data, January 2012, Rev 4.1
Copyright 2012 Wolfson Microelectronics plc
1 page  
Production Data
WM8918
BCLK AND LRCLK CONTROL...................................................................................................................................... 90
COMPANDING .............................................................................................................................................................. 91
LOOPBACK ................................................................................................................................................................... 93
DIGITAL PULL-UP AND PULL-DOWN.......................................................................................................................... 93
CLOCKING AND SAMPLE RATES ............................................................................... 95
SYSCLK CONTROL ...................................................................................................................................................... 97
CONTROL INTERFACE CLOCKING ............................................................................................................................ 97
CLOCKING CONFIGURATION ..................................................................................................................................... 98
DMIC / DAC CLOCK CONTROL ................................................................................................................................... 98
OPCLK CONTROL ........................................................................................................................................................ 99
TOCLK CONTROL ........................................................................................................................................................ 99
DAC OPERATION AT 88.2K / 96K.............................................................................................................................. 100
FREQUENCY LOCKED LOOP (FLL) .......................................................................... 101
FREE-RUNNING FLL CLOCK ..................................................................................................................................... 105
GPIO OUTPUTS FROM FLL ....................................................................................................................................... 105
EXAMPLE FLL CALCULATION................................................................................................................................... 106
EXAMPLE FLL SETTINGS.......................................................................................................................................... 107
GENERAL PURPOSE INPUT/OUTPUT (GPIO) ......................................................... 108
IRQ/GPIO1................................................................................................................................................................... 108
BCLK/GPIO4................................................................................................................................................................ 109
INTERRUPTS.............................................................................................................. 110
USING IN1L AND IN1R AS INTERRUPT INPUTS...................................................................................................... 114
CONTROL INTERFACE.............................................................................................. 115
CONTROL WRITE SEQUENCER............................................................................... 117
INITIATING A SEQUENCE.......................................................................................................................................... 117
PROGRAMMING A SEQUENCE ................................................................................................................................ 118
DEFAULT SEQUENCES ............................................................................................................................................. 121
START-UP SEQUENCE.............................................................................................................................................. 121
SHUTDOWN SEQUENCE........................................................................................................................................... 123
POWER-ON RESET.................................................................................................... 125
QUICK START-UP AND SHUTDOWN........................................................................ 127
QUICK START-UP (DEFAULT SEQUENCE).............................................................................................................. 127
FAST START-UP FROM STANDBY ........................................................................................................................... 127
QUICK SHUTDOWN (DEFAULT SEQUENCE)........................................................................................................... 128
SOFTWARE RESET AND CHIP ID............................................................................. 129
REGISTER MAP ................................................................................................ 130
REGISTER BITS BY ADDRESS ....................................................................... 134
APPLICATIONS INFORMATION ...................................................................... 173
RECOMMENDED EXTERNAL COMPONENTS ......................................................... 173
MIC DETECTION SEQUENCE USING MICBIAS CURRENT..................................... 175
PACKAGE DIMENSIONS.................................................................................. 177
IMPORTANT NOTICE ....................................................................................... 178
ADDRESS.......................................................................................................... 178
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PD, Rev 4.1, January 2012
5
5 Page 
Production Data
INPUT SIGNAL PATH
PGA and Microphone Boost
PARAMETER
Minimum PGA gain setting
Maximum PGA gain setting
Single-ended to differential
conversion gain
PGA gain accuracy
Mute attenuation
Equivalent input noise
WM8918
TEST CONDITIONS
L_MODE/R_MODE= 00b or 01b
L_MODE/R_MODE= 10b
L_MODE/R_MODE= 00b or 01b
L_MODE/R_MODE= 10b
L_MODE/R_MODE= 00b
L_MODE/R_MODE= 00b
Gain -1.5 to +6.7dB
L_MODE/R_MODE= 00b
Gain +7.5 to +28.3dB
L_MODE/R_MODE= 1X
Gain +12 to +24dB
L_MODE/R_MODE= 1X
Gain +27 to +30dB
all modes of operation
L_MODE/R_MODE= 00b or 01b
MIN
-1
-1.5
-1
-1.5
TYP
-1.55
+12
+28.28
+30
+6
100
30
214
MAX
+1
+1.5
+1
+1.5
UNIT
dB
dB
dB
dB
dB
µVrms
nV/√Hz
OUTPUT SIGNAL PATH
Stereo Playback to Headphones - DAC input to HPOUTL+HPOUTR pins with 15 load
Test conditions: HPOUTL_VOL = HPOUTR_VOL = 111001b (0dB)
PARAMETER
SYMBOL
TEST CONDITIONS
Output Power (per Channel)
Po 1% THD
RLoad= 30
MIN
1% THD
RLoad= 15
DC Offset
Signal to Noise Ratio
Total Harmonic Distortion + Noise
Channel Separation
Channel Level Matching
Power Supply Rejection Ratio
SNR
THD+N
PSRR
DC servo enabled,
calibration complete.
A-weighted
RL=30; Po=2mW
RL=30; Po=20mW
RL=15; Po=2mW
RL=15; Po=20mW
1kHz signal, 0dBFS
10kHz signal, 0dBFS
1kHz signal, 0dBFS
217Hz, 100mVpk-pk
1kHz, 100mV pk-pk
-1.5
90
TYP
28
0.92
-0.76
32
0.69
-3.19
96
-91
-84
-87
-85
100
90
+/-1
75
70
MAX
+1.5
-80
UNIT
mW
Vrms
dBV
mW
Vrms
dBV
mV
dB
dB
dB
dB
dB
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PD, Rev 4.1, January 2012
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet WM8918.PDF ] | |
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