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WM8523 Schematic ( PDF Datasheet ) - Wolfson Microelectronics

Teilenummer WM8523
Beschreibung 24-bit 192kHz Stereo DAC
Hersteller Wolfson Microelectronics
Logo Wolfson Microelectronics Logo 




Gesamt 30 Seiten
WM8523 Datasheet, Funktion
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WM8523
24-bit 192kHz Stereo DAC with 2Vrms Ground Referenced Line Output
DESCRIPTION
The WM8523 is a stereo DAC with integral charge pump
and software control interface. This provides 2Vrms line
driver outputs using a single 3.3V power supply rail.
The device features ground-referenced outputs and the use
of a DC servo to eliminate the need for line driving coupling
capacitors and effectively eliminate power on pops and
clicks.
The device is controlled and configured either via the
I2C/SPI compliant serial control interface or a hardware
control interface.
The device supports all common audio sampling rates
between 8kHz and 192kHz using all common MCLK fs
rates. Master and Slave modes are available and de-
emphasis is also supported.
The WM8523 has a 3.3V tolerant digital interface, allowing
logic up to 3.3V to be connected.
The device is available in a 20-lead TSSOP package.
FEATURES
High performance stereo DAC with ground referenced line
driver
Audio Performance
106dB SNR (‘A-weighted’)
-89dB THD @ -1dBFS
Digital Volume control ranging from -100dB to +12dB
120dB mute attenuation
All common sample rates from 8kHz to 192kHz supported
I2C/SPI compatible and hardware control modes
Data formats: LJ, RJ, I2S, DSP
De-emphasis supported
Maximum 1mV DC offset on Line Outputs
Pop/Click suppressed Power Up/Down Sequencer
AVDD and LINEVDD +3.3V ±10% allowing single supply
20-lead TSSOP package
Operating temperature range: -40°C to 85°C
APPLICATIONS
Consumer digital audio applications requiring 2Vrms output
Set Top Box
Digital TV
DVD Players
Games Consoles
A/V Receivers
WOLFSON MICROELECTRONICS plc
Production Data, August 2013, Rev 4.2
Copyright 2013 Wolfson Microelectronics plc






WM8523 Datasheet, Funktion
WM8523
Production Data
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or
beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically
susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling
and storage of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
AVDD, LINEVDD
Voltage range digital inputs
Voltage range analogue inputs
Temperature range, TA
Storage temperature after soldering
Notes
1. Analogue grounds must always be within 0.3V of each other.
2. LINEVDD and AVDD must always be within 0.3V of each other.
MIN
-0.3V
LINEGND -0.3V
AGND -0.3V
-40°C
-65°C
MAX
+4.5V
LINEVDD +0.3V
AVDD +0.3V
+125°C
+150°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Analogue supply range
Ground
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AVDD, LINEVDD
2.97 3.3 3.63
V
AGND, LINEGND
0V
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PD, Rev 4.2, August 2013
6

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WM8523 pdf, datenblatt
WM8523
CONTROL INTERFACE TIMING – SPI MODE
SPI mode is selected by connecting the CIFMODE pin high.
Production Data
Figure 5 Control Interface Timing – SPI Control Mode (Read Cycle)
Test Conditions
LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, TA=+25°C
PARAMETER
Program Register Input Information
SCLK rising edge to CSB falling edge
SCLK falling edge to CSB rising edge
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDA to SCLK set-up time
SDA to SCLK hold time
SDOUT propagation delay from SCLK falling edge
Pulse width of spikes that will be suppressed
Table 4 Control Interface Timing –SPI Control Mode
SYMBOL
tCSU
tCHO
tSCY
tSCL
tSCH
tDSU
tDHO
tDL
tps
MIN
TYP
MAX
UNIT
40 ns
40 ns
160 ns
64 ns
64 ns
20 ns
40 ns
5 ns
2 8 ns
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PD, Rev 4.2, August 2013
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12 Page





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