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WM8782A Schematic ( PDF Datasheet ) - Wolfson Microelectronics

Teilenummer WM8782A
Beschreibung Stereo ADC
Hersteller Wolfson Microelectronics
Logo Wolfson Microelectronics Logo 




Gesamt 20 Seiten
WM8782A Datasheet, Funktion
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24-Bit, 192kHz Stereo ADC
WM8782A
DESCRIPTION
The WM8782A is a high performance, low cost stereo
audio ADC designed for recordable media applications.
The device offers stereo line level inputs along with two
control input pins (FORMAT, IWL) to allow operation of the
audio interface in three industry standard modes. An
internal op-amp is integrated on the front end of the chip to
accommodate analogue input signals greater than 1Vrms.
The device also has a high pass filter to remove residual
DC offsets.
WM8782A offers a Slave mode clocking scheme. A stereo
24-bit multi-bit sigma-delta ADC is used with 128x, 64x or
32x over-sampling, according to sample rate. Digital audio
output word lengths from 16-24 bits and sampling rates
from 8kHz to 192kHz are supported.
The device is a hardware controlled device and is supplied
in a 20-lead SSOP.
The device is available over a functional temperature range of
-40°C to +85°C
BLOCK DIAGRAM
FEATURES
SNR 100dB (‘A’ weighted @ 48kHz)
THD -93dB (at –1dB)
Sampling Frequency: 8 – 192kHz
Slave Clocking Mode
System Clock (MCLK): 128fs, 192fs, 256fs, 384fs, 512fs,
768fs
Audio Data Interface Modes
- 16-24 bit I2S, 16-24 bit Left, 16-24 bit Right Justified
Supply Voltages
- Analogue: 2.7 to 5.5V
- Digital core: 2.7V to 3.6V
20-lead SSOP package
Accelerated Lifetime Screened Devices available.
APPLICATIONS
Recordable DVD Players
Personal Video Recorders
STB
Studio Audio Processing Equipment
Automotive
WOLFSON MICROELECTRONICS plc
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Production Data, April 2010, Rev 4.8
Copyright ©2010 Wolfson Microelectronics plc






WM8782A Datasheet, Funktion
WM8782A
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Digital supply range
Analogue supply range
Ground
Operating temperature range
SYMBOL
DVDD
AVDD
DGND,AGND
TA
TEST CONDITIONS
WM8782SEDS,
WM8782SEDS/R
WM8782SEDS,
WM8782SEDS/R
WM8782SEDS,
WM8782SEDS/R
Notes:
1. Digital supply DVDD must never be more than 0.3V greater than AVDD.
MIN
2.7
2.7
-40
Production Data
TYP
MAX
UNIT
3.6 V
5.5 V
0V
+85 °C
ELECTRICAL CHARACTERISTICS
Test Conditions
DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode
unless otherwise stated.
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC Performance – WM8782SEDS, WM8782SEDS/R (+25˚C)
Full Scale Input Signal Level
(for ADC 0dB Input)
1.0 Vrms
Input resistance, using
recommended external resistor
network on p22.
10 k
Input capacitance
20 pF
Signal to Noise Ratio
SNR
weighted,
93 100
(see Terminology note 1,2,4)
@ fs = 48kHz
dB
Unweighted, 98 dB
@ fs = 48kHz
weighted,
98 dB
@ fs = 48kHz,
AVDD = 3.3V
Signal to Noise Ratio
(see Terminology note 1,2,4)
SNR
weighted,
@ fs = 96kHz
98
dB
Unweighted, 98 dB
@ fs = 96kHz
weighted,
98 dB
@ fs = 96kHz
AVDD = 3.3V
Total Harmonic Distortion
THD
1kHz, -1dB Full Scale
@ fs = 48kHz
-93
dB
1kHz, -1dB Full Scale
@ fs = 96kHz
-93
dB
1kHz, -1dB Full Scale
@ fs = 192kHz
-92
dB
Dynamic Range
DNR
-60dBFS
93 100
dB
Channel Separation
(see Terminology note 4)
1kHz Input
90 dB
Channel Level Matching
1kHz signal
0.1 dB
Channel Phase Deviation
1kHz signal
0.0001
Degree
Power Supply Rejection Ratio
PSRR
1kHz 100mVpp, applied
to AVDD, DVDD
50
dB
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PD, April 2010, Rev 4.8
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WM8782A pdf, datenblatt
WM8782A
Production Data
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 5 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before an LRCLK
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 6 Right Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following an LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
Figure 7 I2S Audio Interface (assuming n-bit word length)
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PD, April 2010, Rev 4.8
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