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PDF RJK0630JPE Data sheet ( Hoja de datos )

Número de pieza RJK0630JPE
Descripción Silicon N-Channel MOS FET
Fabricantes Renesas 
Logotipo Renesas Logotipo



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No Preview Available ! RJK0630JPE Hoja de datos, Descripción, Manual

RJK0630JPE
Silicon N Channel MOS FET
High Speed Power Switching
Features
For Automotive application
AEC-Q101 compliant
Low on-resistance : RDS(on) = 6.2 mΩ typ.
Capable of 4.5 V gate drive
Low input capacitance : Ciss = 2100 pF typ.
Outline
RENESAS Package code: PRSS0004AE-B
(Package name: LDPAK(S)-(1) )
4
123
1G
Absolute Maximum Ratings
Item
Drain to source voltage
Gate to source voltage
Drain current
Drain peak current
Body-drain diode reverse drain current
Body-drain diode reverse drain peak current
Avalanche current
Avalanche energy
Channel dissipation
Channel temperature
Storage temperature
Notes: 1. PW 10 μs, duty cycle 1%
2. Tch = 25°C, Rg 50 Ω
3. Tc = 25°C
4. AEC-Q101 compliant
Symbol
VDSS
VGSS
ID
ID (pulse) Note1
IDR
IDR (pulse) Note1
I Note2
AP
E Note2
AR
Pch Note3
Tch Note4
Tstg
Thermal Impedance Characteristics
Channel to case thermal impedance θch-c: 1.76°C/W
Preliminary Datasheet
R07DS0340EJ0100
Rev.1.00
Apr 18, 2011
2, 4
D
1. Gate
2. Drain
3. Source
4. Drain
S
3
Value
60
±20
75
300
75
300
35
105
85
175
–55 to +150
(Ta = 25°C)
Unit
V
V
A
A
A
A
A
mJ
W
°C
°C
R07DS0340EJ0100 Rev.1.00
Apr 18, 2011
Page 1 of 6

1 page




RJK0630JPE pdf
RJK0630JPE
Normalized Transient Thermal Impedance vs. Pulse Width
10
Preliminary
Vin
15 V
1 D=1
0.5
0.2
0.1
0.1 0.05
0.01
0.02
1shot pulse
0.01
10 μ
100 μ
1m
θch – c(t) = γs (t) θch – c
θch – c = 1.76°C/W, Tc = 25°C
PDM
D
=
PW
T
PW
T
10 m
100 m
1
10
Pulse Width PW (s)
Avalanche Test Circuit
VDS
Monitor
Rg
L
IAP
Monitor
D. U. T
50 Ω
VDD
Avalanche Waveform
EAR = 1 L IAP2
2
VDSS
VDSS VDD
IAP
ID
V (BR)DSS
VDS
VDD
0
Switching Time Test Circuit
Vin Monitor
Rg
D.U.T.
Vout
Monitor
RL
Vin
10 V
VDS
= 30 V
Switching Time Waveform
90%
Vin
Vout
10%
10%
10%
td(on)
90%
tr
90%
td(off)
tf
R07DS0340EJ0100 Rev.1.00
Apr 18, 2011
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